Senior PCB Design Engineer, High-Speed Digital

The challenge

The next server platform routes 12 channels of DDR5-6400 and 128 lanes of PCIe Gen5 on a 20-layer board. Signal integrity simulations show 3 channels failing eye mask at the receiver.

Role overview

You design the PCBs that high-performance servers are built on. Routing high-speed digital interfaces, running signal integrity simulations, and coordinating with mechanical and thermal teams to get boards from schematic through production. The eye diagrams at 32 GT/s don't lie -- either the channel works or it doesn't.

Specializations

Technical requirements

• BSEE or equivalent experience in PCB design
• 8+ years designing high-speed digital PCBs, with 4+ years on server or networking platforms
• Expert Cadence Allegro or Altium skills for complex multi-layer board design
• Proficiency in signal integrity simulation tools (Keysight ADS, Ansys SIwave, or Cadence Sigrity)
• Experience with DDR4/DDR5 and PCIe Gen4/Gen5 interface routing and validation
• Understanding of high-speed digital design principles: impedance control, return path management, crosstalk

Key responsibilities

• Design multi-layer (16-24 layer) PCBs for high-performance server platforms using Cadence Allegro
• Route high-speed interfaces: DDR5, PCIe Gen5, CXL, and Ethernet (up to 112G PAM4 SerDes)
• Perform signal integrity analysis using Keysight ADS or Ansys HFSS for channel compliance verification
• Develop stackup definitions and impedance control strategies for mixed signal density boards
• Collaborate with ASIC teams on package-to-board co-design and breakout optimization
• Support board bring-up and debug using oscilloscopes, TDR, and BERT equipment

Compensation & Benefits

• Base salary: $150,000 - $180,000
• Annual bonus 10%
• Home lab equipment stipend ($3,000)
• Hybrid schedule (2 days on-site for lab access)
• 401(k) with 5% match