Principal FPGA Architect, High-Speed Data Processing

The challenge

The next-gen receiver needs to process multi-tens-of-Gbps downlink data in real time using Xilinx Versal ACAP devices. The current architecture falls short of the throughput target.

Role overview

FPGA architecture for high-throughput signal processing in communication systems. Defining the signal processing pipeline, designing RTL modules, and driving implementation through timing closure on Versal ACAP devices where every nanosecond of pipeline latency matters.

Specializations

Technical requirements

• MSEE with focus on digital signal processing or FPGA design
• 12+ years in FPGA design, with 5+ years on high-throughput signal processing applications
• Expert-level Xilinx Vivado design flow including synthesis, implementation, and timing analysis
• Experience with high-speed serial transceivers (GTY/GTM at 25+ Gbps per lane)
• Strong DSP background: FFT, FIR filtering, polyphase channelizers, MIMO beamforming
• Proficiency in VHDL or SystemVerilog for RTL design

Key responsibilities

• Define FPGA architecture for high-throughput signal processing systems targeting Xilinx Versal ACAP devices
• Design channelization, beamforming, and demodulation pipelines processing multi-tens-of-Gbps aggregate data rates
• Implement high-speed transceiver interfaces (GTY/GTM) for multi-lane data ingestion at 28-58 Gbps per lane
• Develop resource estimation models and performance predictions for new architecture proposals
• Drive timing closure on large FPGA designs using Vivado with custom floorplanning and pipelining strategies
• Mentor FPGA engineers on advanced implementation techniques and verification methodologies

Compensation & Benefits

• Base salary: $200,000 - $235,000
• Annual bonus 12%
• Patent bonus program ($5,000 per filing)
• 9/80 compressed work schedule
• Tuition reimbursement for graduate programs