Senior ASIC Design Engineer, AI Accelerator

The challenge

The third-gen chip needs 100 TOPS at under 15W. The second-gen datapath was designed for CNNs. Transformer workloads have fundamentally different memory access patterns and the current architecture leaves 40% of the MAC array idle during attention computations. The datapath needs a ground-up redesign.

Role overview

RTL design for the compute datapath of an AI inference accelerator. MAC arrays, on-chip memory hierarchy, and the data movement architecture that determines whether the chip hits its TOPS/W target or misses it. The decisions made in this role show up directly in the product's power and performance spec sheet -- and in customer benchmarks against the competition.

Specializations

Technical requirements

• MSEE with focus on digital design or computer architecture
• 7+ years in ASIC RTL design, with experience on at least 2 tapeouts at 7nm or below
• Expert SystemVerilog RTL coding and design skills
• Understanding of AI/ML workload characteristics and accelerator architecture trade-offs
• Experience with lint, CDC, and synthesis tools (Synopsys, Cadence)
• Familiarity with power analysis tools and low-power design techniques

Key responsibilities

• Design and implement RTL for AI inference accelerator compute datapaths using SystemVerilog
• Architect on-chip memory hierarchy (SRAM, register files) optimized for transformer workload access patterns
• Implement configurable MAC array architectures that support INT8, INT4, and FP16 data types
• Perform micro-architectural trade-off analysis for area, power, and performance
• Collaborate with verification team on design-for-verification strategies and functional coverage plans
• Support synthesis and physical design teams on timing closure and power optimization

Compensation & Benefits

• Base salary: $175,000 - $220,000
• Equity (ISO options, 4-year vest, early-stage valuation)
• Annual bonus 10-15%
• Hybrid schedule (3/2)
• Relocation support for Bay Area