Contract Physical Design Engineer, Advanced-Node SoCs

The challenge

The client block arrives with the floorplan half-inherited, utilization already tight, and a tapeout date set before the netlist existed. Timing closure is the job: analyze the timing challenges, identify the critical paths, and drive the block through placement, CTS, and routing until STA, EM/IR signoff, and physical verification (DRC/LVS) all agree. The client ships the silicon. You close the block.

Role overview

Physical design at the block level, RTL synthesis to GDSII on advanced nodes (5nm, 3nm, or newer): floorplanning, placement, clock tree synthesis, routing, and timing closure in a Cadence Genus and Innovus implementation flow, with signoff tools (PT, ICV) closing STA and physical verification. This is contract work at a design-services firm. The blocks belong to fabless clients, the tapeout crunch is real, and the rate reflects closure ownership, not a staffing passthrough. Tcl and Python automation is assumed, not aspirational.

Specializations

Technical requirements

• BSEE or MSEE
• 8+ years in physical design, with blocks closed at 5nm, 3nm, or newer through multiple tapeouts
• Expert with Cadence Genus and Innovus for RTL to GDSII implementation
• Strong STA depth: SDC constraints, RC correlation, extraction, and critical paths
• Experience delivering low power designs using UPF on advanced nodes
• Tcl and Python scripting depth for flow automation

Preferred qualifications

• Experience with UPF promotion/pushdown and power grid design
• Exposure to top-level SoC integration and SoC hierarchy planning
• DFM checks and closure experience ahead of tapeout
• Track record delivering blocks through client signoff flows under tapeout crunch

Key responsibilities

• Execute RTL synthesis for complex ASIC and SoC designs using Cadence Genus
• Develop and improve floorplans using Cadence Innovus, ensuring efficient utilization and routing
• Drive the physical design flow on block-level designs: placement, clock tree synthesis (CTS), routing, and timing closure
• Analyze timing challenges, identify critical paths, and recommend design improvements to close static timing analysis (STA)
• Run timing, IR and EM analysis and closure, plus physical verification (DRC/LVS/Antenna), against signoff flows
• Develop and maintain automation flows using Tcl, Python, and Shell

Compensation & Benefits

• Hourly rate: $100-107/hour W2 ($208,000 - $222,560 annualized)
• 12-month engagement with extension through tapeout
• Hybrid schedule
• Equipment (workstation, monitors) provided