Senior ASIC Design Engineer, AI Accelerator
An AI hardware startup with a shipping product and designing the next-generation architecture.
Semiconductor company developing chiplet-based architectures for high-performance computing. The next-generation HPC product uses 3D-stacked chiplets with hybrid bonding at leading-edge pitch.
Reports to the VP of Advanced Packaging. Eight packaging engineers and three reliability engineers form the advanced packaging group.
Hybrid bonding at leading-edge pitch is producing yield loss from bonding voids. Developing the process and inspection methodology to bring this below production thresholds.
You lead the development of advanced packaging technologies for chiplet-based products. Process development, reliability testing, and design rule definition enabling next-generation 3D integration -- the work that determines whether chiplet architectures deliver on their performance-per-watt promises.
An AI hardware startup with a shipping product and designing the next-generation architecture.
A communications equipment manufacturer building high-throughput signal processing systems on large-scale FPGA platforms.
A semiconductor manufacturer ramping a new advanced-node fab with 300mm wafer production in the US.
Staff Packaging Engineer, Advanced 3D Integration
$260K - $305K base