A fabless chip company designing custom SoCs at an advanced node and taping out on a leading foundry process.
Eight DFT and verification engineers inside the design org. You report to the DFT Lead.
Tapeout is on the clock, the design is multiple millions of gates, and the test data volume blows past tester memory unless the compression ratio holds. ATPG coverage on stuck-at is close, but transition-fault coverage still needs work and the at-speed patterns have to fit the same budget. The DFT has to be right at RTL, because there is no fixing it on the tester.
Design-for-test architecture and signoff for custom silicon: scan insertion, embedded compression, and MBIST inserted at RTL, with ATPG coverage closed against the tapeout schedule. The day-to-day is scan chain stitching, pushing the scan compression ratio so test data volume fits tester memory, and signing off stuck-at, transition, and path-delay coverage. DFT here is an upstream design discipline, not a tester activity downstream.
An AI hardware startup with a shipping product and designing the next-generation architecture.
A communications equipment manufacturer building high-throughput signal processing systems on large-scale FPGA platforms.
A semiconductor manufacturer ramping a new advanced-node fab with 300mm wafer production in the US.
Senior Design-for-Test (DFT) Engineer
$190K - $225K base
