Contract ASIC Verification Engineer

The challenge

Tapeout is in 6 months and functional coverage is at 78%. The target is 95% across all coverage groups. You will drive coverage closure for the packet processing pipeline and memory subsystem.

Role overview

UVM testbenches and verification environments that prove the chip works before it goes to the fab. Constrained random stimulus, coverage model development, and closing coverage gaps on a tapeout schedule where every week of slip costs the company a quarter of revenue.

Specializations

Technical requirements

• MSEE with focus on digital design or verification
• 5+ years in ASIC verification using UVM methodology
• Expert SystemVerilog skills for testbench development
• Experience with functional coverage-driven verification methodologies
• Proficiency with industry verification tools (VCS, Xcelium, Questa)
• Experience with formal verification tools (JasperGold, VC Formal)

Key responsibilities

• Develop UVM-based verification environments for networking ASIC subsystems
• Write constrained random stimulus and directed test cases for packet processing and memory controllers
• Build and refine functional coverage models to track verification completeness
• Drive coverage closure from 78% to 95%+ across assigned coverage groups
• Perform formal verification using JasperGold or VC Formal for protocol compliance
• Debug RTL failures using waveform analysis and assertion-based debugging

Compensation & Benefits

• Hourly rate: $105-130/hour ($218,400 - $270,400 annualized)
• 6-month contract with extension through tapeout
• Remote work with occasional on-site visits
• Equipment (workstation, monitors) provided